1. Field of the Invention
The present invention relates to a driver circuit device, and more specifically to circuit construction of a driver circuit device used for a high-speed small-amplitude interface which can transmit signals at high speed.
2. Description of the Prior Art
Recently, an LVDS (low voltage differential signal) interface has been identified as an interface for transmitting small amplitude signals at high speed. This LVDS interface is standardized as differential small-amplitude interfaces by P1596. 3 which is one of the small standardization committees of IEEE. This standard is explained in detail in Document IEEE Draft Standard for Low-voltage Scalable Coherent Interface (SCI) Draft 1. 20! (Jul. 13, 1995).
FIG. 5 is a conceptual view for assistance in explaining this LVDS interface.
In the drawing, a driver block 3 and a receiver block are connected by a going transmission line 8 and a returning transmission line 9. The going and returning transmission lines 8 and 9 constitute a so-called equilibrium transmission line having the same electrical characteristics. Further, the major feature of this LVDS interface is to transmit one signal through these two transmission lines.
The driver block 3 has a driver chip 1 for inputting a signal from an input terminal 10. A high voltage supply 14 is connected to the driver chip 1 via a high voltage drive resistor 5, and a low voltage supply 15 is connected to the same driver chip 1 via a low voltage drive resistor 6. Here, the resistance value R.sub.OH of the high voltage drive resistor 5 is about 50.OMEGA. and the resistance value R.sub.OL of the low voltage drive resistor 6 is about 50.OMEGA..
The receiver block 4 has a receiver chip 2 for outputting a signal from an output terminal 12. A high voltage supply 29 is connected to the receiver chip 2, and a low voltage supply 30 is connected to the same receiver chip 2. Here, the resistance value R.sub.T of an end resistor 7 is about 100.OMEGA.. Further, the impedance of each of the going and returning transmission lines 8 and 9 is 50.OMEGA..
In the construction as described above, the driver chip 1 forms a differential signal on the basis of an input signal applied to the input terminal 10 in such a way that a potential difference can be generated between the going and returning transmission lines 8 and 9. On the other hand, the receiver chip 2 converts the differential signal generated between the going and returning transmission lines 8 and 9 into a CMOS level and outputs the converted CMOS level signal from the output terminal 12.
The principle of the LVDS is to direct a signal current I.sub.s generated on the driver chip (1) side to flow through a loop formed by the equilibrium transmission line (i.e., both the going and returning transmission lines 8 and 9) and the end resistor 7 on the receiver chip (2) side, to generate a signal voltage across the end resistor 7 for signal transmission. Here, the signals of "0" and "1" can be discriminated by switching the current direction of the signal current I.sub.s.
In the circuit construction as described above, since the current flowing through the driver chip 1 is roughly constant and further since the signal currents I.sub.s flowing through the going and returning transmission lines 8 and 9 are the same with respect to each other in magnitude but opposite to each other in direction, the total current flowing through the equilibrium transmission line is "0", so that the signal current I.sub.s hardly fluctuates.
On the other hand, when a current switchable-type comparator is used as the receiver chip 2, it is possible to consider that the current flowing the whole transmission system hardly fluctuates.
The above-mentioned characteristics of the driver circuit imply that the noise generated due to current fluctuations in the transmission system is small. In addition, since the interference between the transmission lines between two adjacent ports and/or the simultaneous switching interference between two LSIs, this LVDS interface is suitable for use to transmit high speed signals higher than 200 MHz.
In this connection, in the LVDS interface, the signal current I.sub.s is about 3 mA, and the voltage across the end resistor 7 is about 300 mV.
In the circuit construction as shown in FIG. 5, the driver block 3 can be realized by a circuit as shown in FIG. 6.
In FIG. 6, an input signal is applied from the input terminal 10 through an inverter 16. After having passed through a buffer circuit composed of two transistors 50 and 51, an output of the inverter 16 is further inverted by another inverter 19, and then inputted to two gates of two transistors 52 and 57. At the same time, the output of the inverter 16 is inputted to two gates of two transistors 53 and 56 via two other inverters 17 and 18 without inversion. Further, the buffer circuit composed of the two transistors 50 and 51 serves to compensate for a time delay of the signal inverted by the inverter 17 for transmitting the signal in parallel to the buffer circuit (50 and 51).
Two drains of the transistors 52 and 56 are connected to a drain of a transistor 54. A source of the transistor 54 is connected to the high voltage supply 14, and a gate of the transistor 54 is connected to a bias input terminal 21.
On the other hand, two sources of the transistors 53 and 57 are connected to a drain of a transistor 55. A gate of the transistor 55 is connected to its drain, and a source thereof is connected to the low voltage supply 15.
A source of the transistor 52 and a drain of the transistor 53 are connected in common to an output terminal 13. The output terminal 13 is connected to the going transmission line 8 shown in FIG. 5.
On the other hand, a source of the transistor 56 and a drain of the transistor 57 are connected in common to an output terminal 13B. The output terminal 13B is connected to the returning transmission line 9 shown in FIG. 5.
In the above-mentioned circuit construction, the transistor 54 to which a bias BIAS is applied through the bias input terminal 21 serves as the high voltage drive resistor 5 shown in FIG. 5, and the transistor 55 serves as the low voltage drive resistor 6 shown in FIG. 5.
On the other hand, the receiver block 4 shown in FIG. 5 can be realized by a circuit as shown in FIG. 7.
In FIG. 7, an input terminal 11 connected to the going transmission line 8 is connected to a gate of a transistor 60. On the other hand, an input terminal 11B connected to a returning transmission line 9 is connected to a gate of a transistor 60. Two sources of the transistors 60 and 66 are connected in common to a drain of a transistor 61. A gate of the transistor 61 is connected to a bias input terminal 22, and a source thereof is connected to a high voltage supply 29.
A drain of the transistor 60 is connected to a source and a gate of a transistor 62, a gate of a transistor 63, a drain of a transistor 64, and a gate of a transistor 59, respectively.
A drain of the transistor 66 is connected to a drain and a gate of a transistor 65, a gate of the transistor 64, a drain of a transistor 63, and a gate of a transistor 68, respectively. Further, sources of the transistors 62, 63, 64, 65, 59 and 68 are all connected to the low voltage supply 30.
A drain of the transistor 59 is connected to a drain and a gate of the transistor 58, and a gate of the transistor 67. On the other hand, a source of the transistor 58 is connected to the high voltage supply 29.
Further, a source of the transistor 67 is connected to the high voltage supply 29, and a drain of the transistor 67 is connected to a drain of the transistor 68. Further, two drains of the transistors 67 and 68 are connected to an output terminal 12.
Further, in the driver block 3 and the receiver block 4 shown in FIGS. 6 and 7, respectively, a current bias circuit for determining current is used, respectively. FIG. 8 shows an example of the current bias circuit.
In FIG. 8, a bias output terminal 31 is derived from a gate and a drain of a transistor 73, and a drain of a transistor 74. A source of the transistor 73 is connected to the high voltage supply, and a source of a transistor 74 is connected to the low voltage supply.
A gate of the transistor 74 is connected to a drain of a transistor 71 and a drain and a gate of a transistor 72. A source of the transistor 71 is connected to the high voltage supply, and a source of the transistor 72 is connected to the low voltage supply.
A gate of the transistor 71 is connected a gate and a drain of a transistor 69, and a gate of the transistor 72 is connected to a gate of a transistor 70. A source of the transistor 69 is connected to the high voltage supply, and a source of the transistor 70 is connected to the low supply voltage.
Further, an output signal of the bias output terminal 31 of the current bias circuit shown in FIG. 8 is used as the bias input applied to the bias input terminal 21 of the driver block shown in FIG. 6 and as the bias input applied to the bias input terminal 22 of the receiver block shown in FIG. 7.
In the circuit construction as described above, when a high speed signal higher than 400 MHz is transmitted, since a parasitic capacitance as small as 10 pF is inevitably formed by usually-used pins of a package, this causes a problem as follows: In order to drive such a parasitic capacitance as described above, a signal current as small as 3 to 4 mA is not sufficient. Further, when the signal frequency is high, it is impossible to obtain a signal having a sufficient amplitude between the low and high voltages, that is, between the low and high supply voltage levels. As a result, the signal of the present cycle is shifted to that of the succeeding cycle before the signal level swings full with an amplitude of about 300 mV prescribed by the LVDS interface.
In other words, on the receiver side, since the differential amplitude of the signal is reduced as compared with a predicted DC value, a special circuit for increasing the sensitivity is additionally required. As a result, another problem arises inevitably such that a chip area increases to construct the additional circuit and further the current consumption increases.
Further, in a back plane transmission environment or a cable transmission environment as prescribed by the LVDS, if the differential amplitude drops less than 200 mV, there exists such a possibility that the differential signal is inevitably subjected to the influence of external noise. That is, in order to transmit a high speed signal higher than 400 MHz, it is necessary to take appropriate measures for realizing the high speed operation and for securing the sufficient AC differential amplitude, by charging and discharging the package parasitic capacitance at a sufficiently high speed.